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Energy efficient approximate multipliers compatible with error-tolerant application
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AI
DOI：10.1016/j.compeleceng.2023.109064.png)
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Abstract
En 中文
Multipliers are one of the most commonly used parts in a system, responsible for performing computations, while significantly contributing to power consumption. In this article, by removing the least significant bits, a new architecture is presented to implement 3 multipliers (Mul-1, Mul-2 and Mul-3), in order to reduce complexity and power consumption. Compared to the previous works, Mul-1 has the most accuracy in addition to its low energy consumption, therefore, it has been able to deliver a good trade-off between accuracy and energy consumption. All proposed designs and existing multipliers have been simulated and compared in 7 nm FinFET technology using Hspice tool. Moreover, the accuracy and quality of the proposed approximate multipliers are also evaluated using MATLAB. The results show that Mul-1 and Mul-3 are very efficient in image processing applications. According to the results, Mul-1 outperforms its counterpart by 10%, 50% and 50% in PDP, NMED and MRED, respectively. Furthermore, Mul-3 has satisfactory MSSIM in DSP applications and is better than its counterpart by 23% and 16% in PDP and MRED. Meanwhile, Mul-2 improves PDP by nearly 53% compared to Mul-1 and has the lowest power consumption.
Keywords:
Approximate multiplier
Energy-efficiency
DSP
Compressor
Approximate circuits
Journal
C
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