Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding

Anh Tuan

doi:10.1109/TCSII.2019.2958668

Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding

2020-10-01

11

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AI

A

Anh Tuan

S

Seyed Mohammad Ali Zeinolabedin

T

Tony Tae-Hyoung Kim *

DOI：10.1109/TCSII.2019.2958668

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This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of 0s. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for 0. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 mu W and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V.

Keywords:

Encoding

Sensors

Decoding

Low-power electronics

SRAM cells

Image coding

SRAM

data-aware

ultra-low power

bitline leakage

Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding

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