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Enhanced Efficiency 3D Convolution Based on Optimal FPGA Accelerator
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DOI：10.1109/ACCESS.2017.2699229.png)
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Abstract
En 中文
This paper presents an enhanced efficiency 3-D convolution operator based on optimal field programmable gate array (FPGA) accelerator platform. The proposed system takes advantages of the intermediate data delay lines, implemented in an FPGA, to avoid loading repetition of the input feature maps. This 3-D convolution accelerator performs 268.07 giga operations per second at 100-MHz operation frequency, with 330-mW power consumption. We experimentally demonstrate the enhanced efficiency of the proposed convolution accelerator, in comparison with the conventional technologies. The proposed 3-D convolution accelerator may find interesting applications in neural networks and video processing.
Keywords:
Accelerator architectures
neural networks
convolution
field programmable gate arrays
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