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Enhancing predictive accuracy using machine learning for network-on-chip performance modeling
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DOI：10.1016/j.compeleceng.2024.110041.png)
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Abstract
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Network-on-Chip (NoC) is a promising, scalable interconnect solution of System-on-Chip (SoC) designs for high-performance computing platforms. The critical metrics, such as latency, throughput, and the number of packets received, directly impact the overall performance of NoCs. However, a cycle-accurate simulator takes considerable execution time with system size. This work proposes a machine learning approach with various regression models to predict critical metrics for network-on-chip-based architectures. The proposed work explores Polynomial regression (PR), Linear regression (LR), and Decision tree regression (DTR) models to predict linear and non-linear performance metrics. The obtained results are compared with the dataset generated from a cycle-accurate simulator. The experimental results showed an accuracy of 99% for linear and up to 98% for non-linear outputs with a maximum speed of around 3600x compared to a cycle-accurate simulator. Testing our model with SPLASH-2 and PARSEC real and synthetic benchmarks outperformed the existing works due to the convincing nature of real traffic.
Keywords:
Cycle-accurate simulator
Performance enhancement
Machine learning
Network-on-chip (NoC)
Regression models
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C
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4.9
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6.7K
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