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Evolution of Stack Architecture and Interconnect Technology for Detector Array Chips
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DOI：10.3390/electronics15122588.png)
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Abstract
En 中文
The detector array chips can be used to capture the transient space-time signal of the pulse radiation field. It is mainly composed of a photoelectric array detector and a readout circuit. However, the metal leads used to connect the detector and the readout circuit have long spacing. This can easily introduce additional delays, resulting in a decrease in the response performance of the chip, which cannot meet the goal of simultaneous transmission of ultra-fast detection signals. In recent years, the rapid development of three-dimensional interconnect technology has enabled the chip to achieve shorter interconnect spacing, smaller parasitic parameters and smaller delay time, thereby improving system response performance. The integrated detector array chips composed of three-dimensional interconnects has the advantages of fast signal interconnection transmission speed, high bandwidth, process compatibility and functional expansion compared with the traditional planar architecture. At the same time, there are some limitations and challenges. Therefore, this paper mainly reviews the evolution characteristics of the stacked architecture of the detector array chips, the process development and the nanosecond-level transmission integration challenges. This paper effectively incorporates the three into a unified framework. This provides a solution for the realization of integrated nanosecond detector array chips. Furthermore, it promotes the application and expansion of the chip in the pulse radiation field diagnosis technology.
Keywords:
array detector
hybrid integration
three-dimensional interconnect
nanosecond peer transmission
ultra-fast detection
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