Fast Decoding ECC for Future Memories

doi:10.1109/JSAC.2016.2603698

Fast Decoding ECC for Future Memories

2016-09-01

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DOI：10.1109/JSAC.2016.2603698

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High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore, we propose an architecture for fast decoding of double and triple ECCs. In our architecture, any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular, the error locator polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here, we describe a gate-level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.

Keywords:

DRAM

nonvolatile memory

phase change memory

error correction codes

Galois fields

block codes

Fast Decoding ECC for Future Memories

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