FIR Filter Design Methodology for Hardware Optimized Implementation

Rizwana Mehboob

doi:10.1109/TCE.2009.5278041

FIR Filter Design Methodology for Hardware Optimized Implementation

2009-08-01

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DOI：10.1109/TCE.2009.5278041

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This paper presents a novel method of FIR filter design for optimized hardware implementation. The FIR filters are extensively employed in a variety of consumer devices like TVs, mobile phones and docking stations. The optimized implementations of FIR filter furnish high quality signal processing at reasonable cost. The paper first analyzes the effects of quantization on frequency response of a filter by successively reducing the number of bits in each coefficient. Empirical analysis of efficient quantization reveals a relationship between the number of bits, number of coefficients and the frequency response. The paper then presents a methodology for an optimized design of an FIR filter for hardware implementation. The proposed approach first designs a filter with certain parameters and then redesigns the same filter with tighter constraints resulting in higher filter order. The coefficients of the improved or over designed filter are then quantized successively with lesser number of bits by an iterative algorithm to a level where its frequency response matches to the original requirements. The synthesis results show that a significant reduction in hardware resources can be achieved using this methodology. The proposed approach has so far not been reported for reduction in hardware resources(1).

Keywords:

Bit Length

Optimization

Quantization

FIR Filter and Hardware Resources

FIR Filter Design Methodology for Hardware Optimized Implementation

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