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Floating-point atomic memory operations
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DOI：10.1016/j.micpro.2026.105276.png)
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Abstract
En 中文
Modern computing systems are increasingly adopting chiplet-based architectures, enabling the integration of different vendor devices, such as Central Processing Units (CPUs), Graphic Processing Units (GPUs), within a single package. These heterogeneous systems require efficient inter-chip synchronization mechanisms, including Atomic Memory Operations (AMOs). However, efficient synchronization demands that all integrated devices support the same AMO capabilities. While GPUs natively support floating-point AMOs (FAMOs), CPUs do not, creating an architectural asymmetry that leads to synchronization inefficiencies. To address this gap, Arm has recently introduced the Large System Floating-point Extension (LSFE), which introduces novel FAMO support to CPUs. This work characterizes and models the impact of FAMOs on graph processing, Machine Learning (ML), and High-Performance Computing (HPC) workloads. Our analysis reveals that a substantial fraction of AMOs target floating-point data and are currently implemented using inefficient compare-and-swap (CAS) built-ins. Replacing CAS-based constructs with hardware native FAMOs significantly improves performance across a wide range of workloads. Furthermore, we examine the trade-offs of executing FAMOs at different levels of the memory hierarchy, comparing execution in private caches (near) versus shared caches (far). Our results show that near FAMOs achieve an average speed-up of 1.3 & times; speed-up, while far FAMOs deliver an average speed-up of 1.5 & times;. Overall, we demonstrate that FAMOs can enable more efficient synchronization across key application domains.
Keywords:
Atomic Memory Operations
Synchronization directives
Cache coherency
Multicore architectures
Chiplet-based architectures
Heterogeneous architectures
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