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FPGA-Based Handwritten Digit Recognition Using 3-D Hop Net and Equilibrium Optimization
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DOI：10.1109/ICJECE.2026.3665570.png)
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Abstract
En 中文
Handwritten digit recognition is an important topic with applications ranging from digitizing historical documents to automating mailroom sorting. In recent years, there has been a rising interest in using specialized hardware accelerators to improve the performance of digit identification systems. Existing FPGA accelerators suffer from degraded energy efficiency during weight matrix multiplication and reduced flexibility due to limited local interconnections among processing elements (PEs). To address the inefficiencies, a novel FPGA accelerator-based 3-D unified crossbar hop net and equilibrium optimization is introduced. This design replaces complex floating-point operations with memristor crossbar array multiplication for efficient computation, connects PEs with a deep pipeline systolic array globally, and reduces memory utilization through unified quantization-based weight merging. The weighted equilibrium optimizer minimizes computation errors during backpropagation, achieving optimized model training. In addition, a 3-D Hopfield neural network enhances handwritten digit recognition accuracy by preserving temporal information and managing data-dependent pathways. The model presents a comprehensive solution to improve accelerator performance in terms of energy efficiency, flexibility, and recognition accuracy.
Keywords:
Space exploration
Radio broadcasting
Frequency modulation
Field programmable gate arrays
Circuits
Very large scale integration
Integrated circuits
Central Processing Unit
High level synthesis
Microprocessors
Memristor crossbar array
pipeline systolic array
unified quantization
weight merge mechanism
weighted equilibrium optimizer
Journal
I
IF:
1.9
Papers:
39
Citations:
310