FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture

Jian Zhang

doi:10.1109/TCSII.2021.3126012

FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture

2022-03-01

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DOI：10.1109/TCSII.2021.3126012

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This brief presents an event-driven spiking multi-kernel convolution architecture for processing address-event representation (AER) streams from dynamic vision sensor (DVS) chips. The processor architecture is designed based on leaky integrate-and-fire (LIF) neural model, and employs pipeline scheme to accelerate data processing. A new scheme for arranging neuron membrane potentials and kernels in memories is proposed, which enables row-by-row kernel processing and accelerates the multi-kernel convolution computation. An FPGA prototype of the proposed architecture is implemented on a Xilinx Zynq FPGA development board with 100 MHz clock frequency. The proposed processor architecture computes 64 filters with configurable kernel size (from 1 x 1 to 32 x 32) on input flow, obtaining the latency of 0.10 us to 10.33 us for convoluting an event, and the energy of 0.12 nJ and 12.08 nJ per event per convolution, respectively.

Keywords:

Neurons

Convolution

Kernel

Program processors

Indexes

Frequency modulation

Field programmable gate arrays

Event-driven

spiking convolution neural network (SCNN)

field programmable gate array (FPGA)

parallel processing

hardware implementation

FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture

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