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GC-BNN: Gain Cell-eDRAM based in-memory Binary Neural Network accelerator
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DOI：10.1016/j.sysarc.2026.103867.png)
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Abstract
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The deployment of Deep Neural Networks (DNNs) on edge devices is limited by the energy overhead of data movement between processing and memory units, known as the von Neumann bottleneck. While Processing-in-Memory (PiM) addresses this by performing computation within memory arrays, current solutions face significant trade-offs: resistive-memory-based PiM suffers from device non-idealities and limited endurance, while SRAM-based architectures lack the density required for large-scale integration. In this work, we propose GC-BNN, a novel in-memory Binary Neural Network (BNN) accelerator based on Gain Cell Embedded DRAM (GC-eDRAM). Leveraging a standard 16 nm CMOS process, GC-BNN utilizes the high-density and decoupled-port characteristics of 3T GC-eDRAM to implement massively parallel bit-wise XNOR operations. We introduce a column-parallel scheme that utilizes complementary weight storage and majority calculation to enable single-cycle binary dot-products, followed by a full precision population count for the output layer resolved through an efficient iterative reference sweep. Unlike existing state-of-the-art accelerators that offload various BNN components to external hardware or software, GC-BNN supports end-to-end in-memory BNN implementation. This includes binary hidden layers, batch normalization, and fully-connected output classification, all executed internally within the memory block. Silicon measurements on a 16 nm test chip demonstrate that GC-BNN achieves a peak energy efficiency of 340 TOPS/W at 500 MHz, establishing GC-eDRAM as a compelling, high-density technology for energy-constrained edge AI inference.
Keywords:
Gain cell embedded DRAM
Processing in memory
Processing using memory
Logic operations in memory
Binary neural networks
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