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Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations
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DOI：10.1109/TCSII.2018.2807362.png)
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Abstract
En 中文
In low-density parity check (LDPC) decoder implementations, the architecture of the node processing units (NPUs) has a significant impact both on the hardware resource requirements and on the processing throughput. Additionally, some NPU architectures impose limitations on the decoder's support for intra- or interstandard LDPC code flexibility at run-time. In this brief, we present a generalised algorithmic method of constructing NPUs that support run-time flexibility while maintaining a low hardware resource requirement and high maximum operating frequency. FPGA-based synthesis results demonstrate that the proposed architecture offers a significantly improved hardware efficiency, when compared to two commonly employed alternatives.
Keywords:
Digital communication
error correction codes
low-density parity check (LDPC) codes
stochastic computing
iterative decoding
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