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Hardware-Friendly Algorithm Optimization and Acceleration for 8K UHD Image and Video Broadcasting
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DOI：10.1109/tbc.2026.3679969.png)
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Abstract
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Efficient implementation plays a critical role for real-time 8K Ultra-High-Definition (UHD) video broadcasting with the new generation video coding standards. Specifically, the more complex Coding Unit (CU) partitioning rules in new standards make it much more challenging to design efficient acceleration strategies. This paper proposes a light-weight hardware-friendly acceleration algorithm for CU partitioning, which is the bottleneck to implementing the Versatile Video Coding (VVC) based real-time intra codec for 8K video broadcasting on hardware platform. According to the CU partitioning rule, we first propose an novel One-Pass framework to determine CU split results, which can effectively reduce time complexity and hardware resources incurred by the original iterative decision process. Second, taking into account the characteristics of hardware platform, the efficient calculation methods based on Map-Reduce model and hardware-oriented optimizations are designed for gradient and histogram difference features required by our One-Pass framework. Finally, we design a reference hardware architecture to validate the effectiveness of the proposed algorithm to support real-time 8K video broadcasting. Besides, a light-weight 8K UHD video dataset including diverse content is also provided to more reliably illustrate the coding performance of our algorithm. Experimental results show that our method is capable of the real-time CU division on Xilinx VU440 FPGA at 200 MHz, where the single-path can support 8K videos at 45 frames per second (fps), and 135 fps also can be achieved with multi-path parallelism. As far as we are aware, the proposed algorithm has attained state-of-the-art performance for the hardware-friendly acceleration of CU partitioning with the least loss in VVC standard.
Keywords:
Fast CU partition
VVC
8K UHD
hardware validation
real-time broadcasting
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