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Hardware friendly deep reservoir computing
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DOI：10.1016/j.neunet.2025.108079.png)
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Abstract
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• We address the challenge of designing hardware-friendly deep reservoir computing architectures. • We propose a hierarchical HF-DESN model with ring reservoir topology and one-to-one inter-reservoir connections. • We demonstrate the feasibility of implementing the model in electronic hardware and confirm its agreement with physics-informed simulations. • We show the performance advantages of deep reservoir setups over shallow models on tasks requiring nonlinear computation and short-term memory.
Keywords:
Reservoir computing
Deep echo state networks
Recurrent neural networks
Neural networks in hardware
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