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HCFR: A pipeline-free hybrid CPU-FPGA acceleration architecture for small-file erasure coding recovery
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DOI：10.1016/j.sysarc.2026.103899.png)
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Abstract
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Distributed storage systems face significant challenges in recovering massive amounts of small files, where the high start-up latency of traditional deep-pipeline hardware and the context-switching overhead of pure software solutions severely constrain real-time performance. To address this issue, this paper proposes HCFR, a hardware-software co-designed hybrid architecture. By constructing a “pipeline-free” FPGA decoder based on pure combinational logic to eliminate pipeline fill and drain overheads, and integrating CPU-based binary decomposition for matrix inversion with a double-buffering latency hiding mechanism, the proposed architecture achieves pipeline-level parallelism. Experimental results show that, for extremely small objects such as 32 Bytes, HCFR achieves up to 18.75 × core decoding speedup over Jerasure and up to 14.30 × over Intel ISA-L. In terms of end-to-end recovery throughput, HCFR achieves up to 14.52 × improvement over Jerasure and up to 7.68 × over Intel ISA-L under the evaluated RS configurations. Furthermore, it achieves approximately 9 × higher energy efficiency over the evaluated CPU-based software implementation, effectively breaking the performance barrier associated with small data block recovery. This study presents an efficient and viable technical pathway for mitigating tail latency in heterogeneous storage systems, offering broad application prospects for next-generation low-latency cloud storage and edge computing infrastructures.
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