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High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm
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DOI：10.1109/TCSI.2024.3492797.png)
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Abstract
En 中文
A multiply-accumulator, often abbreviated as a MAC unit, is central to a multitude of computational tasks, particularly those tasks (such as neural networks) involving array-based mathematical computations. The quest for novel methods to efficiently store and process data in a MAC has become imperative. Recently, ternary logic has attracted significant attention due to its higher information density than conventional binary systems. However, though numerous studies have showcased ternary arithmetic circuits, advancements in ternary-based vector processing have been notably scarce. To bridge this gap, this work undertakes comprehensive study into the optimization of ternary MAC units. Firstly, we propose various ternary approximate algorithms which shows 30%-less power consumption and only 2% computation error when compared with the accurate design. Secondly, we design sophisticated ternary circuits and obtain 74% similar to 80% lower power-delay-product (PDP) than previous works. Finally, we evaluate the proposed ternary MAC unit using both carbon-nanotube field-effect transistor (CNTFET) and silicon-based 180 nm CMOS processes. The simulation results show the ternary circuit is better than binary circuit in terms of both area (similar to 45% less) and power ( similar to 30% less), highlighting its strong potential for practical applications.
Keywords:
Circuits
Multivalued logic
Adders
CNTFETs
Accuracy
Transistors
Encoding
Approximation algorithms
Threshold voltage
Performance evaluation
Ternary logic circuit
multiplying-accumulator
approximation algorithms
Journal
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9.7K
Citations:
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