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High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning
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DOI：10.1109/TCSII.2023.3318352.png)
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Abstract
En 中文
With the vertically stacked configuration and different technology processes imposed by stacked three-dimensional (3D) integration circuits (ICs), the placement problem has become more challenging. In this brief, we develop a high-performance 3D placement engine with physical-aware incremental partitioning for the stacked 3D ICs. We first propose a compact 2D global placement (GP) to find desired locations for all cells in a die, and then present a progressive density-driven partitioning to partition the netlist into two dies. After that, we propose an incremental half-perimeter wirelength (HPWL)-driven partitioning and a 3D GP to alternately optimize the partitioning and placement results. Finally, we present legalization and detailed placement methods to ensure the legality and further improve the solution. Compared with the top 3 teams of the ICCAD 2022 contest, experimental results on the contest benchmarks show that our algorithm achieves the best solution quality for every benchmark in a comparable runtime.
Keywords:
Physical design
placement
partition
3D IC
hybrid bonding technology
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