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High-performance CMOS-compatible self-rectifying memristor for passive array integration
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DOI：10.1103/PhysRevApplied.22.064003.png)
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Abstract
En 中文
The integration of memristor-based devices in large-scale passive arrays necessitates the development of self-rectifying memristors (SRMs). However, existing SRMs face significant challenges in achieving high ON:OFF and self-rectification ratios while maintaining complementary metal-oxide semiconductor (CMOS) compatibility. Here, we present a SRM with a Pt/WO3/WO3-x/TiN structure, which exhibits an impressive rectification ratio (approximately 10(5)), satisfactory ON:OFF ratio (around 103), low operation voltage (2 V), and high stability (>10(6) s, 104 cycles). When incorporated into a 100x100 array, this device achieves a remarkable resistance reading accuracy of 97.3%. Furthermore, by setting the read margin to 10%, the passive array integrated with this device can reach a storage capacity of up to 180.3 Gb. At the same time, we simulate an on-chip convolutional neural network based on a 32x32 passive array, achieving a recognition accuracy of 99.1% for the handwritten digits 0, 1, and 2. The use of CMOS-compatible materials and a simple single-oxide-layer structure can significantly reduce industrial costs. These advancements offer valuable insights for the development of practical and scalable SRMs, paving the way for their widespread integration in large-scale in-memory computing applications.
Keywords:
MEMORY