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High performance dense ring generators
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AI
DOI：10.1109/TC.2006.11.png)
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Abstract
En 中文
This paper presents an enhanced architecture of on-chip pseudorandom test pattern generators, test data decompressors, and test response compactors based on ring generators. The new structure is aimed at improving layout and routing properties while, at the same time, reducing propagation delays introduced by associated phase shifters.
Keywords:
built-in self-test
design for testability
linear feedback shift registers
phase shifters
ring generators
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3.8
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5.3K
Citations:
9.8K
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