.png){kind=icon}
.png){kind=icon}
Return
High-Performance Mixed-Precision Linear Solver for FPGAs
.png){kind=icon}
PRE
AI
DOI：10.1109/TC.2008.89.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
Compared to higher precision data formats, lower precision data formats result in higher performance for computationally intensive applications on FPGAs because of their lower resource cost, reduced memory bandwidth requirements, and higher circuit frequency. On the other hand, scientific computations usually demand highly accurate solutions. This paper seeks to utilize lower precision data formats whenever possible for higher performance without losing the accuracy of higher precision data formats by using mixed-precision algorithms and architectures. First, we analyze the floating-point performance of different data formats on FPGAs. Second, we introduce mixed-precision iterative refinement algorithms for linear solvers and give an error analysis. Finally, we propose an innovative architecture for a mixed-precision direct solver for reconfigurable computing. Our results show that our mixed-precision algorithm and architecture significantly improve the performance of linear solvers on FPGAs.
Keywords:
Reconfigurable computing
supercomputing
floating point
data formats
iterative refinement
Journal
IF:
3.8
Papers:
5.3K
Citations:
9.8K