.png){kind=icon}
.png){kind=icon}
Return
High-Precision MUX-Based Digital Delay Interpolators Based on a Novel Transistor Sizing Algorithm
.png){kind=icon}
PRE
AI
DOI：10.1109/TCSII.2025.3571482.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
We propose a technique able to reduce nonlinearity in multiplexer-based digital delay interpolators, by optimizing transistor sizing. In our approach, we adjust the driving capabilities of each MOSFET within multiplexers to minimize the interpolation error, measured in terms of integral nonlinearity (INL). Implementation results in 28nm CMOS technology with interpolation factors of 8, 16 and 32 demonstrate the effectiveness of the technique. Post-layout simulations show that the proposed method is able to reduce the INL by more than 90% with only a small increase in area, while the power dissipation is substantially unchanged. Multi-corner analyses demonstrate consistent results under process, voltage, and temperature variations.
Keywords:
Digital delay interpolation
INL
transistor sizing
Journal
I
IF:
4.9
Papers:
8.8K
Citations:
2.5W