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High Step-Up IPOS DCDC Converter Based Efficiency Optimization Control Strategy
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DOI：10.1109/TIE.2022.3177809.png)
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Abstract
En 中文
This article introduces a symmetrical, high step-up, input-parallel output-serial (IPOS), dc-dc converter based on voltage multiplier (VM) cells and active clamp circuits to obtain a very high voltage conversion ratio. The VM using a switched capacitor and the coupled inductor makes high voltage gain achievable, which results in reduced voltage stress on power switches. Meanwhile, the IPOS structure also makes great improvements in the above aspects. Importantly, by incorporating active clamp circuits, not only voltage spikes caused by leakage inductance are restrained but also the clamped circuit plays a role in energy transfer to boost the gain. Especially, zero voltage switching for all switches can be obtained. Furthermore, the optimization control strategy is proposed to further improve the overall efficiency. A detailed mathematical analysis of the proposed converter is conducted for systematizing its design. Finally, a prototype of 768 W output power and the 480 V output voltage is implemented to verify the excellent performance of the proposed converter.
Keywords:
DC-DC converter
efficiency optimization
high step-up
input-parallel output-serial (IPOS)
Journal
IF:
7.2
Papers:
1.8W
Citations:
9.8W