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High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator
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DOI：10.1007/s11554-018-0832-6.png)
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Abstract
En 中文
Real-time operation and low-power dissipation in video coding systems have become important research challenges, especially in mobile devices with limited battery and computational resources. Given the variety of applications able to manipulate videos and the growing number of video coding standards, current devices are expected to provide native support to multiple coding standards. Although state-of-the-art coding requires a wide set of tools focusing on coding efficiency, major tools are usually present in different standards with limited differences. Therefore, implementing dedicated architectures for each standard tool is an inefficient approach at both development time and silicon area. Fractional Motion Estimation (FME) and Motion Compensation (MC) are among the most computation-intensive tasks within video codecs and are used in all major video coding standards. Thus, this paper presents a multi-standard sample interpolator hardware design for the MC and FME with full support to MPEG-2, MPEG-4, H.264/AVC, HEVC, AVS, and AVS2. The proposed design is capable of UHD 8K (Ultra High Definition -4320p@60fps) real-time interpolation when synthesized using a 45nm standard-cell library. The circuit footprint occupies 65,508 mu m(2) and the power dissipation ranges from 14.58 to 65.316mW for MPEG-2 and AVS2 operation modes, respectively.
Keywords:
Multi-standard interpolator
Motion compensation
Fractional motion estimation
Video coding
Hardware design
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