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High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm
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DOI：10.1109/TCSI.2012.2190668.png)
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Abstract
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Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which only has 0.05-0.1 dB performance loss against the sum-product algorithm, a highly efficient decoder architecture is developed. Compared with the existing works, our design has three advantages. First, the design increases the parallelism and throughput of the decoder by three to four times. The implementation results for the decoder show high throughput of 64 Mbps at 15 iterations. Second, this design saves memory usage by 38% to 76%. Third, this design shows 2.64 X area efficiency improvement even compared with the most state-of-the-art design.
Keywords:
Decoder architecture
error control coding
low-density
parity-check (LDPC) codes
non-binary
VLSI design
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