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Highly Scalable Parallel Arithmetic Coding on Multi-Core Processors Using LDPC Codes
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DOI：10.1109/TCOMM.2011.101011.110071.png)
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Abstract
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We describe a highly scalable parallel arithmetic coder for Markov inputs suitable for implementation on modern multi-core processors. The algorithm divides the input into interleaved sub-sequences which can be then processed independently on different processing units using LDPC-based Slepian-Wolf coding. Experimental simulations show good scalability of the proposed algorithm while also maintaining good compression performance. Notably, when compared with traditional parallel arithmetic coding, the proposed method maintains a much higher efficiency both respect to the entropy limit as well as in terms of the ability to distribute computations across multiple cores without performance loss.
Keywords:
Arithmetic coding
Slepian-Wolf coding
multi-core architecture
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