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Impact of Switching Transients and High-Frequency Oscillations on SiC MOSFET Gate-Source Voltage: Analysis and Mitigation
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DOI：10.1109/JESTIE.2025.3640431.png)
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Abstract
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The lower switching transition times of silicon carbide (SiC) mosfets result in higher dv/dt across their device drain-source terminals during switching. The high dv/dt further causes high-frequency (HF) oscillation in the drain-source voltage. These affect the gate-source voltage of the off-state device in a commonly used phase-leg configuration where a top and bottom device are alternatively switching. The first part of the article presents a detailed analysis of the origin of the HF oscillations, linking them to the energy stored in specific parasitic elements in the power loop. Existing literature typically neglects the effect of HF oscillations on the gate-source voltage and analyses it only using the dv/dt transition. In the second part of the article, an improved analysis of the gate-source voltage is carried out by including the effect of HF oscillations. Further, a more accurate representation of the dv/dt transition is suggested and used for the analysis. It is shown that there is a significant difference in the gate-source voltage peaks when the effect of the HF oscillations is accounted for. Using this analysis, the article in the last part of the work shows the effectiveness of the active-miller clamp technique in mitigating the effects of power loop oscillations on the gate-source voltage of the off-state device. Experimental results are provided to support the theoretical analysis.
Keywords:
Logic gates
Oscillators
MOSFET
Silicon carbide
Hafnium
Capacitance
Transient analysis
Threshold voltage
Switches
Prevention and mitigation
Active-miller clamp (AMC) technique
false turn-on
high-frequency (HF) oscillations
negative gate bias voltage
silicon carbide (SiC) mosfet
switching transients
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