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Implementing a chaotic cryptosystem in a 64-bit embedded system by using multiple-precision arithmetic
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DOI：10.1007/s11071-019-04802-3.png)
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Abstract
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This paper proposes a new chaotic cryptosystem for the encryption of very high-resolution digital images based on the design of a digital chaos generator by using arbitrary precision arithmetic. This can be taken as an alternative to reduce the dynamic degradation that chaotic models present when they are implemented in digital devices and to increase the security of the cryptosystems. The obtained results show that when using high-precision arithmetic, the generated sequences provide good randomness and security during a greater number of iterations of the implemented chaotic maps in comparison with the generated sequences by using the standard of simple precision or double precision according to the IEEE 754 standard for floating-point arithmetic. The proposed method does not require high-cost hardware for increasing the numerical accuracy and security. As an advantage versus other recent works, using high precision, in relation to the methods that use simple precision or double precision, it awards an exponential increase in the key space. In this manner, it is demonstrated that using multiple-precision arithmetic, a key space of 233,268 or higher can be obtained, depending on the level of high precision configured. The security analysis confirms that the proposed chaotic cryptosystem is secure and robust against several known attacks, as well as statistical tests of NIST and TestU01, proving that high-precision arithmetic helps to enhance the security of the cryptosystems.
Keywords:
Chaotic cryptography
Digital degradation
floating-point arithmetic
Arbitrary precision arithmetic
Embedded system
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