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Improved first-order time-delay tanlock loop architectures
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DOI：10.1109/TCSI.2006.880316.png)
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Abstract
En 中文
This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a I number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation.
Keywords:
architecture
loop
performance
tanlock
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5.2
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9.9K
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