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Improving Multi-Level Flash Memory with SHare Coding for Faster and More Efficient Data Access∗
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DOI：10.1587/transfun.2025TAP0003.png)
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Abstract
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Flash memory is gaining prominence in modern storage systems due to its ability to provide large-capacity and high-speed data access. Multi-level flash memory, which stores multiple bits per cell, has become particularly important for increasing storage density. However, this technology faces a significant challenge: as the number of bits per cell increases, more read threshold voltages are required, resulting in slower access speeds. Previous work by Sharon et al. introduced random inputoutput (RIO) codes to address this issue by reducing the number of read thresholds to one. While RIO codes successfully improve read speeds, they sacrifice storage capacity compared to conventional uncoded multilevel flash memory. To overcome these limitations, we propose SHare Coding (SHC), a novel multi-cell coding scheme that maintains maximum storage efficiency while reducing the number of required read thresholds. We demonstrate that our proposed SHC enables single-read operation for multi-level cell (MLC) flash memory using three cells, achieving both high speed and full storage capacity. Furthermore, we provide a formal definition of SHC and present a comprehensive error rate analysis, showing that the bit error rates of SHC are comparable to those of conventional MLC systems. Our results indicate that SHC offers a practical solution for improving flash memory performance without compromising storage capacity.
Keywords:
flash memory
multi-level cell
coding
read threshold
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