Improving SSD Read Latency via Coding

Hyegyeong Park

doi:10.1109/TC.2020.2978823

Improving SSD Read Latency via Coding

2020-12-01

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DOI：10.1109/TC.2020.2978823

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We study the potential enhancement of the read access speed in high-performance solid-state drives (SSDs) by coding, given speed variations across the multiple flash interfaces and assuming occasional local memory failures. Our analysis is based on a queuing model that incorporates both read request failures and NAND element failures. The NAND element failure in the present context reflects various limitations on the memory element level such as bad blocks, dies or chips that cannot be corrected by error control coding (ECC) typically employed to protect pages read off the NAND cells. Our analysis provides a clear picture of the storage-overhead and read-latency trade-offs given read failures and NAND element failures. We investigate two different ways to mitigate the effect of NAND element failures using the notion of multi-class jobs with different priorities. A strong motivation for this work is to understand the reliability requirement of NAND chip components given an additional layer of failure protection, under the latency/storage-overhead constraints.

Keywords:

Encoding

Maintenance engineering

Decoding

Parity check codes

Sensors

Error correction codes

Bandwidth

NAND flash memory

solid-state drives

NAND component failures

distributed storage

latency analysis

queuing theory

error-control coding

Improving SSD Read Latency via Coding

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