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In-Filter Computing for Designing Ultralight Acoustic Pattern Recognizers
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DOI：10.1109/JIOT.2021.3109739.png)
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Abstract
En 中文
We present a novel in-filter computing framework that can be used for designing ultralight acoustic classifiers for use in the smart Internet of Things (IoT). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a support vector machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on a field-programmable gate array (FPGA)-based IoT platform. While the proposed in-filter computing framework is general enough, in this article, we demonstrate this concept using a cascade of an asymmetric resonator with inner hair cells (CAR-IHCs)-based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series FPGA. We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only 1.5k lookup tables (LUTs) and 2.8k flip-flops (FFs), a significant improvement over other approaches.
Keywords:
Support vector machines
Kernel
Hardware
Acoustics
Feature extraction
Training
Field programmable gate arrays
Cochlea
edge computing
field-programmable gate array (FPGA)
Internet of Things (IoT)
neuromorphic
support vector machine (SVM)
Journal
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