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In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology
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DOI：10.1109/TCSI.2019.2945617.png)
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Abstract
En 中文
In-memory computing architectures present a promising solution to address the memory- and the power-wall challenges by mitigating the bottleneck between processing units and storage. Such architectures incorporate computing functionalities inside memory arrays to make better use of the large internal memory bandwidth, thereby, avoiding frequent data movements. In-DRAM computing architectures offer high throughput and energy improvements in accelerating modern data-intensive applications like machine learning etc. In this manuscript, we propose a vector addition methodology inside DRAM arrays through functional read enabled on local word-lines. The proposed primitive performs majority-based addition operations by storing data in transposed manner. Majority functions are achieved in DRAM cells by activating odd number of rows simultaneously. The proposed majority based bit-serial addition enables huge parallelism and high throughput. We validate the robustness of the proposed in-DRAM computing methodology under process variations to ascertain its reliability. Energy evaluation of the proposed scheme shows 21.7X improvement compared to normal data read operations in standard DDR3-1333 interface. Moreover, compared to state-of-the-art in-DRAM compute proposals, the proposed scheme provides one of the fastest addition mechanisms with low area overhead ( 1 of DRAM chip area). Our system evaluation running the ${k}$ -Nearest Neighbor ( ${k}$ NN) algorithm on the MNIST handwritten digit classification dataset shows 11.5X performance improvement compared to a conventional von-Neumann machine.
Keywords:
In-memory computing
DRAM
processing-in-memory
von-Neumann bottleneck
bit-serial addition
k-NN acceleration
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