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Integer multipliers with overflow detection
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DOI：10.1109/TC.2006.126.png)
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Abstract
En 中文
This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay.
Keywords:
computer arithmetic
high-speed arithmetic algorithms
combinational logic
overflow detection
multiplication
Journal
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3.8
Papers:
5.3K
Citations:
9.8K
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