InTeRail: A test architecture for core-based SOCs

Dimitri Kagaris

doi:10.1109/TC.2006.27

InTeRail: A test architecture for core-based SOCs

2006-02-01

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DOI：10.1109/TC.2006.27

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A flexible test architecture for embedded cores and all interconnects in a System-on Chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM paths. It also provides for dynamic wrapper reconfiguration. Algorithms that minimize the use of extra interconnects for the TAM path formation are presented and evaluated.

Keywords:

system-on-chip test

cores

test access mechanism

design for testability

InTeRail: A test architecture for core-based SOCs

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