.png){kind=icon}
.png){kind=icon}
Return
Investigating Floating-Gate Topology Influence on van der Waals Memory Performance
.png){kind=icon}
OA
AI
H
Q
C
J
Y
张
DOI：10.3390/nano15090666.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
As a critical storage technology, the material selection and structural design of flash memory devices are pivotal to their storage density and operational characteristics. Although van der Waals materials can potentially take over the scaling roadmap of silicon-based technologies, the scaling mechanisms and optimization principles at low-dimensional scales remain to be systematically unveiled. In this study, we experimentally demonstrated that the floating-gate length can significantly affect the memory window characteristics of memory devices. Experiments involving various floating-gate and tunneling-layer configurations, combined with TCAD simulations, were conducted to reveal the electrostatic coupling behaviors between floating gate and source/drain electrodes during shaping of the charge storage capabilities. Fundamental performance characteristics of the designed memory devices, including a large memory ratio (82.25%), good retention (>50,000 s, 8 states), and considerable endurance characteristics (>2000 cycles), further validate the role of floating-gate topological structures in manipulating low-dimensional memory devices, offering valuable insights to drive the development of next-generation memory technologies.
Keywords:
van der Waals transistor
floating-gate memory
memory window
electrostatic coupling
Journal
N
IF:
4.3
Papers:
2.2W
Citations:
8.1W
Organization
No organization information available
Cited Papers