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Investigating memory system energy behavior using software and hardware optimizations
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DOI：10.1155/2001/70310.png)
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Abstract
En 中文
Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms and three widely used compiler optimization techniques used to reduce the memory system energy. Our presentation is in two parts. First, we focus on a set of memory-intensive benchmark codes and investigate their memory system energy behavior due to data accesses under hardware and compiler optimizations. Then, using four motion estimation codes, we look at the influence of compiler optimizations on the memory system energy considering the overall impact of instruction and data accesses.
Keywords:
memory system energy
block buffering
sub-banking
compiler optimizations
on-chip caches
sub-banks