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Investigation of TMDC-based impact-ionization field effect transistor (I2-FET) for low power logic
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DOI：10.1016/j.rinp.2026.108713.png)
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Abstract
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• Continuous device scaling demands steep-slope, low-power logic transistors beyond the Boltzmann limit. • DC I-V, dynamic C-V, and CMOS inverter operations are comprehensively analyzed for TMDC-based I2-FETs. • An anomalous gate capacitance peak is first observed at the turn-on of the WSe2-based I2-FET. • Enhanced ION dominates the CMOS inverter switching delay despite the CGG,peak anomaly. • EDP analysis demonstates the low-power operation of the proposed I2-FET.
Keywords:
Impact-ionization FET
Steep slope devices
Low power application
TMDC
TCAD simulation
Switching delay
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