Line-Coalescing DRAM Cache

doi:10.1016/j.suscom.2020.100449

Line-Coalescing DRAM Cache

2021-03-01

3

PRE

AI

DOI：10.1016/j.suscom.2020.100449

Original

Original request for help

Save

Abstract

En 中文

Die-stacked DRAM has emerged as an effective approach to address the memory bandwidth wall as it offers much higher bandwidth than off-chip DRAM. It is typically used along with much larger off-chip DRAM to form a hybrid memory system with sufficient capacity and abundant bandwidth. Lots of research activities have been drawn to exploit the potentials of such memory systems. One of the approaches is to use Die-stacked DRAM as a cache of off-chip DRAM. Judicious mechanisms have been proposed to manage these on-chip DRAM caches with tailored line sizes, fetch sizes, replacement policies, and allocation mechanisms. One such example is Footprint Cache [16] which uses 2 KB lines but populates each line with only referenced 64B blocks to avoid transferring dead blocks. Doing so significantly reduces the traffic between on-chip DRAM and off-chip DRAM. In this paper, we propose to extend the idea of Decoupled Sector Cache [32] to the DRAM Cache by allowing multiple sparsely populated lines to be coalesced and stored in one DRAM Cache line (we call it Line-Coalescing DRAM Cache (LCDC)). Our experimental results show that LCDC can effectively increase the utilization of on-chip DRAM and provide 16.7% performance boost over prior designs. In addition, it is orthogonal with many existing DRAM Cache techniques and can work with them to increase the performance improvement to 27.5% and achieve 89.1% of the performance of an ideal DRAM Cache design.

Keywords:

DRAM Cache

Die-stacked DRAM

3D DRAM

HBM

HMC

Line-Coalescing DRAM Cache

Abstract

AI Summary

Journal

Organization