.png){kind=icon}
.png){kind=icon}
Return
Linearized Analysis and Quantization Error Minimization for Mid-Rise TDCs: A Tutorial
.png){kind=icon}
OA
AI
DOI：10.1109/TCSI.2024.3524422.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
The mid-rise time-to-digital converter (TDC), e.g., a binary (bang-bang) phase detector and other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked loop (DPLL) because of the design simplicity and ultra-low consumption in terms of area and power. However, its hard quantization nonlinearity makes it nontrivial to estimate its linearized gain and the power of the quantization error (QE) that it introduces, and hence can make the linearized analysis at the DPLL-system level inaccurate. This tutorial paper formulates a minimum-mean-square-error estimator that is used to provide an accurate linearized analysis of the TDC; it takes into account the interaction between the quantization characteristic of the TDC and the statistical properties of the input jitter of a frequency synthesizer in both integer-N and fractional-N modes. A strategy for minimizing the TDC's QE is provided; so-designed TDCs with equidistant quantization thresholds are able to achieve optimum jitter minimization at both the TDC and DPLL levels. Finally, the effective linear operating region of such TDCs is derived, which explains when the hard quantizer can be regarded as an almost linear PD and when not. Behavioral simulations at the TDC-block and DPLL-system levels underpin our analysis.
Keywords:
Quantization (signal)
Jitter
Minimization
Frequency synthesizers
Detectors
Accuracy
Phase locked loops
Estimation error
Circuits
Tutorials
Time-to-digital converter (TDC)
digital phase locked loop (DPLL)
minimum mean square error (MMSE)
linear analysis
quantization error
frequency synthesizer
PLL
Journal
IF:
5.2
Papers:
9.7K
Citations:
2.2W