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Logic Encryption for Resource Constrained Designs
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DOI：10.1109/ACCESS.2021.3059163.png)
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Abstract
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Logic Encryption is a hardware security technique that protects integrated circuit designs that are fabricated at untrusted pure play foundries from being pirated or maliciously modified. In the technique, logic gates are added to the design that are driven by an added key input bus, such that the correct behavior of the circuit is recovered with only the exact correct key input pattern. However, the power, performance, and area (PPA) cost of implementing logic encryption has often been ignored in the literature in favor of increasing the level of security provided. This has proved to be a significant hurdle in transitioning the method to use in commercial-grade designs and a systematic methodology of constraining the cost of logic encryption is needed. In this paper, we propose a generalized Constraint-Directed Logic Encryption (CDLE) methodology. In CDLE, the potential design space of encrypted versions of a circuit is searched to apply logic encryption under PPA constraints. Two example CDLE methods are proposed. The first is a concurrent tree search method which uses commercial tools to sample designs for their PPA cost and determine the optimal encryption strategy. In this method, PPA cost is accurately analyzed at the cost of heavy runtime. The second is a machine learning approach which estimates the PPA cost to predict the optimal encryption strategy. The machine learning model developed in this work is limited, but the results are promising as a direction for study in logic encryption. Detailed experimental results evaluating both methods are presented.
Keywords:
Encryption
Measurement
Integrated circuits
Logic gates
Hardware
Machine learning
Foundries
Hardware security
integrated circuits
logic encryption
cost metrics
logic synthesis
machine learning
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