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Longest Path Selection Based on Path Identifiers
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DOI：10.1109/ACCESS.2024.3357754.png)
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Abstract
En 中文
A small delay defect adds a small extra delay to the propagation time of a signal through a gate or line. Small delay defects can occur during fabrication or during the lifetime of a chip. When a path with small delay defects has a delay that exceeds its permissible value based on the clock period, timing failures may occur. To detect small delay defects, test generation procedures target path delay faults that are associated with the longest paths. Storage of paths can have a significant memory overhead. To avoid this overhead, it was shown earlier that paths can be associated with unique integer identifiers. The identifiers are based on a labeling of the circuit lines with two integer labels that are computed in linear time. This article suggests a third integer label, also computed in linear time, that allows a subset of the longest paths to be identified based only on their integer identifiers. The third label ensures that the longest path has identifier 0, and shorter paths have larger identifiers. Thus, with an exception discussed and addressed in the article, it is possible to target the longest paths for test generation by targeting the paths with identifiers 0, 1, 2, $\ldots $ . An identifier needs to be translated into a physical path only when it is targeted for test generation. The article applies the new labeling to benchmark circuits and presents experimental results to demonstrate its effectiveness.
Keywords:
Delays
Labeling
Object recognition
Logic gates
Circuit faults
Test pattern generators
Fault diagnosis
Launch-on-capture tests
launch-on-shift tests
path delay faults
path selection
test generation
