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Low Complexity 2D Adaptive Image Processing Algorithm and Its Hardware Implementation
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DOI：10.1109/TCE.2017.014996.png)
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Abstract
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Digital image processing (DIP) algorithms used in consumer electronics products have high computational complexities. Therefore, in this paper, we propose a novel low complexity 2D adaptive DIP algorithm. The proposed algorithm reduces computational complexities of 2D DIP algorithms by exploiting pixel correlations in input image without reducing quality of output image. We also designed a low energy 2D adaptive DIP hardware implementing the proposed algorithm. The proposed hardware is verified to work correctly on an FPGA board. It has significantly less energy consumption than original 2D DIP hardware. Therefore, it can be used especially in portable consumer electronics products.
Keywords:
Median Filter
Gaussian Blur
Image Sharpening
Hardware Implementation
FPGA
Low Energy
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