Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm

doi:10.1109/TCSI.2021.3136222

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm

2022-04-01

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DOI：10.1109/TCSI.2021.3136222

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The compressive sensing (CS) based sparse vector coding (SVC) method is one of the promising ways for the next-generation ultra-reliable and low-latency communications. In this paper, we present advanced algorithm-hardware co-optimization schemes for realizing a cost-effective SVC decoding architecture. The previous maximum a posteriori subspace pursuit (MAP-SP) algorithm is newly modified to relax the computational overheads by applying novel residual forwarding and LLR approximation schemes. A fully-pipelined parallel hardware is also developed to support the modified decoding algorithm, reducing the overall processing latency, especially at the support identification step. In addition, an advanced least-square-problem solver is presented by utilizing the parallel Cholesky decomposer design, further reducing the decoding latency with parallel updates of support values. The implementation results from a 22nm FinFET technology showed that the fully-optimized design is 9.6 times faster while improving the area efficiency by 12 times compared to the baseline realization.

Keywords:

Static VAr compensators

Decoding

Computer architecture

Reconstruction algorithms

Matching pursuit algorithms

Encoding

Ultra reliable low latency communication

Compressive sensing

subspace pursuit

parallel architecture

ultra reliable and low latency communications

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm

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