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Low Computational Complexity Delay Estimation Algorithm for Digital Predistortion
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DOI：10.1109/TCSII.2024.3362709.png)
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Abstract
En 中文
In practical scenarios, digital predistortion (DPD) systems are typically deployed on hardware platforms. However, the current time delay alignment algorithm, a critical component of DPD processing, requires substantial hardware resource allocation. Consequently, this brief introduces a novel delay estimation algorithm aimed at simplifying the time alignment segment, including both integer and fractional elements. The integer alignment method is established on an adaptive filter framework, while the fractional component leverages a recursive least square (RLS) algorithm, based on a Farrow structure, to circumvent extensive matrix calculations. The complexity analysis, coupled with experimental results show that the proposed methods not only preserve high accuracy but also substantially diminish computational resource demands by 88.7% and 87.8%, respectively, when compared with two prevailing delay estimation techniques. This enhancement notably augments the performance of hardware-based DPD systems.
Keywords:
Delay estimation
Adaptive filters
Finite impulse response filters
Time-domain analysis
Predistortion
Hardware
Filtering algorithms
Digital predistortion (DPD)
time synchronization
time domain
farrow structure
Journal
I
IF:
4.9
Papers:
8.8K
Citations:
2.5W
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