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Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding
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DOI：10.1109/TCSI.2011.2107271.png)
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Abstract
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This paper presents a low-energy asynchronous interleaver for clockless fully parallel low-density parity-check (LDPC) decoding. The proposed data-transmission circuit based on a half-duplex single-track protocol makes it possible to realize a wire-efficient asynchronous interleaver with small energy consumption. Moreover, a data-monitoring system adaptively shuts down the asynchronous data-transmission circuit if not necessary, which reduces the number of data transmissions and, hence, the energy consumed. The clockless decoder with the proposed asynchronous interleaver is evaluated using a (1056,528) irregular LDPC code under a 90-nm CMOS process. As a result, the energy dissipation per uncoded bit at E-b/N-o of 5 dB becomes 54 pJ/bit with an uncoded throughput of 45.5 Gbps under a postlayout simulation. This represents a 92% decrease in energy per bit and a 1143% in throughput increase with respect to our previous clockless LDPC decoder.
Keywords:
Asynchronous circuits
forward error control (FEC)
iterative decoding
low-density parity-check (LDPC) codes
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