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Low power content-addressable memory for FPGA implementation
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DOI：10.1080/00207217.2026.2637035.png)
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Abstract
En 中文
Content-Addressable Memory (CAM) is a vital component in various computing systems, enabling rapid data retrieval based on content rather than memory addresses. However, traditional CAM designs often suffer from high power consumption, limiting their applicability in low-power and energy-efficient applications. This study proposes a novel Low Power Content-Addressable Memory (LPCAM) optimised for Field-Programmable Gate Array (FPGA) platforms. The proposed LPCAM design leverages advanced circuit and architectural techniques to minimise power consumption while maintaining efficient search and storage capabilities. Power-aware optimisations, such as selective precharge and dynamic power gating, significantly reduce energy consumption during both idle and active states. Moreover, careful optimisation of the transistor-level design and layout further enhances the power efficiency. To validate the LPCAM design, it was implemented on an FPGA platform and subjected to extensive simulations. The results show a 45% reduction in total power consumption and a 43.75% improvement in energy efficiency compared to traditional CAM implementations while maintaining competitive performance metrics. On comparing with existing CAM architecture implementations, the proposed LPCAM implementation is highly resource-efficient and is suitable for power-sensitive applications.
Keywords:
Content addressable memory (CAM)
low power
energy efficient
matchline and FPGA
Journal
I
IF:
1.1
Papers:
146
Citations:
1.6K