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Low power data processing system with self-reconfigurable architecture
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DOI：10.1016/j.sysarc.2006.12.008.png)
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Abstract
En 中文
In this paper, a low power data processing system with a self-reconfigurable architecture and USB interface is presented. A single FPGA performs all processing and controls the multiple configurations without any additional elements, such as microprocessor, host computer or additional FPGAs. This architecture allows high performance with very low power consumption, a comprehensive alternative to microprocessor or DSP systems. In addition, a hierarchical reconfiguration system is used to support a large number of different processing tasks without the power consumption penalty of a big local configuration memory. Due to its simplicity and low power, this data processing system is especially suitable for portable applications, reducing the disadvantage of FPGAs against ASICS in low power consumption applications [A. Amara, F. Amiel, T. Ea, FPGA vs. ASIC for low power applications, Microelectronics Journal 37 (8) (2006) 669-677]. (c) 2007 Elsevier B.V. All rights reserved.
Keywords:
low power consumption
dynamic partial reconfiguration
digital signal processing
image processing
FPGAs
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