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Low Power Design through Frequency-Optimized Runtime Micro-architectural Adaptation
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DOI：10.1109/ICCD46524.2019.00057.png)
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Abstract
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This paper presents a method to generate a variety of micro-architectures for a given hardware accelerator mapped onto reconfigurable fabric optimized for different operating frequencies. The most optimal micro-architecture is then loaded onto the fabric for a given operating frequency in order to minimize the power consumption. State-of-the-art FPGAs are runtime reconfigurable and provide multiple clock domains. This enables these devices to reconfigure any accelerator mapped on them and their frequencies at runtime. At the same time, FPGA vendors have embraced High-Level Synthesis (HLS) to increase the design productivity and help designers with limited hardware development skills to program these devices. One of the advantages of HLS over traditional RT-level hardware design is that HLS allows to automatically generate micro-architectures with unique area, performance and power trade-offs by setting different synthesis options, which is impractical or very time consuming at the RT-level. This work leverages these two features and investigates the benefit of adapting the micro-architecture of hardware accelerators mapped onto a reconfigurable fabric at runtime when the operating frequency changes to reduce the power consumption, while maximizing the throughput. To enable the frequency-aware micro-architectural adaptation we also propose a simple micro-architectural resource manager and show that the overhead in terms of area and delay is negligible. We conduct two sets of experiments. The first shows that our proposed approach leads to faster circuits which consume less power than just statically scaling the frequency of the fastest micro-architecture for a variety of different test cases. The second case, presents case study of a face detection application mapped onto a battery-operated wireless camera sensor node powered by solar cells.
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FPGAS
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