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Low-power selective pattern compression for scan-based test applications
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DOI：10.1016/j.compeleceng.2013.11.028.png)
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Abstract
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The ever-increasing test data volume and test power consumption are the two major issues in testing of digital integrated circuits. This paper presents an efficient technique to reduce test data volume and test power simultaneously. The pre-generated test sets are divided into two groups based on the number of unspecified bits in each test set. Test compression procedure is applied only to the group of test sets which contain more unspecified bits and the power reduction technique is applied to the remaining test sets. In the proposed approach, the unspecified bits in the pre-generated test sets are selectively mapped with Os or is based on their effectiveness in reducing the test data volume and power consumptions. We also present a simple decoder architecture for on-chip decompression. Experimental results on ISCAS'89 benchmark circuits demonstrate the effectiveness of the proposed technique compared with other test-independent compression techniques. (C) 2013 Elsevier Ltd. All rights reserved.
Keywords:
TEST DATA VOLUME
RUN-LENGTH
SYSTEM
ARCHITECTURE
CAPTURE
SCHEME
SHIFT
TIME
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