Low-Power TinyOS Tuned Processor Platform for Wireless Sensor Network Motes

Rajkumar Raval

doi:10.1145/1754405.1754408

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Low-Power TinyOS Tuned Processor Platform for Wireless Sensor Network Motes

2010-06-10

Rajkumar Raval *

Carlos Fernández

Chris J. Bleakley

DOI：10.1145/1754405.1754408

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Abstract

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In this article we describe a low-power processor platform for use in Wireless Sensor Network (WSN) nodes (motes). WSN motes are small, battery-powered devices comprised of a processor, sensors, and a radio frequency transceiver. It is expected that WSNs consisting of large numbers of motes will offer long-term, distributed monitoring, and control of real-world equipment and phenomena. A key requirement for these applications is long battery life. We investigate a processor platform architecture based on an application-specific programmable processor core, System-On-Chip bus, and a hardware accelerator. The architecture improves on the energy consumption of a conventional microprocessor design by tuning the architecture for a suite of TinyOS-based WSN applications. The tuning method used minimizes changes to the instruction set architecture facilitating rapid software migration to the new platform. The processor platform was implemented and validated in an FPGA-based WSN mote. The benefits of the approach in terms of energy consumption are estimated to be a reduction of 48% for ASIC implementation relative to a conventional programmable processor for a typical TinyOS application suite without use of voltage scaling.

Keywords:

Design

Performance

Embedded system design

hardware-software codesign

Wireless Sensor Network

low power processor

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